This invention relates to a folding stage for a folding analog-to-digital converter, the folding stage comprising:
an input terminal for receiving an input voltage to be folded;
reference means having a plurality of consecutive reference terminus for providing ascending different reference voltages;
a first summing node and a second summing node;
a plurality of differentially coupled transistor pairs, each one of the pairs comprising a current source, a first transistor having a first main electrode coupled to the current source and a control electrode coupled to the input terminal and a second transistor having a first main electrode coupled to the current source and a control electrode coupled to a respective one of the consecutive reference terminus, the second main electrode of the first transistor of consecutive transistor pairs being coupled alternately to the first summing node and the second summing node, and the second main electrode of the associated second transistor being coupled alternately to the second summing node and the first summing node.
Such a folding stage is known from U.S. Pat. No. 4,386,339. Folding stages are commonly used in analog-to-digital (A/D) converters.
Important considerations in designing an A/D converter are speed, component count and resolution. Full flash conveyers have a relatively simple architecture. To convert an analog input voltage into an N-bit digital output code, a full flash conveyer normally employs 2.sup.N -1 input comparators for comparing the input voltage with 2.sup.N -1 corresponding reference voltages. The principal disadvantage of the full flash converter is the high component count due to the large number of input comparators. Several schemes have been proposed to reduce the number of components.
The folding technique is one of the schemes for reducing component count. Folding architectures have been successfully implemented in very high speed bipolar A/D converters. See R. van de Grift et al., "An 8-bit Video ADC Incorporating Folding and Interpolating Techniques", IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 6, December 1987, pp 944-953. Also see R. van de Plassche et al., "An 8-bit 100-MHz Full-Nyquist Analog-to Digital Converter", IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, December 1988, pp 1334-1344. The basic principles of the folding architecture are extensively explained in these references. A folding A/D converter comprises a number of folding stages, each comprising a set of differential pairs responding to the input voltage and a corresponding set of reference voltages. The outputs of the differential pairs are combined in such a way as to generate one or more single ended folding signals or pairs of complementary folding signals having a repetitive rounded triangular or sine wave shape as a function of the input voltage. The folding signals of the folding stages are supplied to respective one's of a group of sample latches for converting the folding signals to a group of least significant bits of the digital output code. The most significant bits are supplied by a group of coarse comparators which operate on the input voltage along a separate channel. In this way the number of latches can be reduced considerably. The number of latches is reduced by the number of times the input signal is folded by the folding stages. However, each latch requires its own folding signal and each folding stage requires as many differential pairs as the number of times the signal has been folded. The more efficient use of the latches is therefore offset by an increasing number of differential pairs in the folding stages. As also known from the afore-mentioned IEEE-references, the number of folding stages can be reduced by interpolating between the folding signals of the folding stages to generate additional folding signals without the need for more folding stages. In this way the interpolation reduces the number of folding stages by the interpolation factor. A combined folding and interpolating architecture results in a compact low-power A/D converter.
The folding technique is also useful in other A/D architectures. In U.S. Pat. No. 4,386,339 a direct flash A/D converter is disclosed having independent parallel A/D converters for each bit. Each independent bit-encoder has a folding stage coupled to a single comparator which provides a bit of directly encoded compact binary output. In this way conversion from thermometer code to binary code is not needed.
A folding stage thus can be used in several distinct A/D converter architectures. However, a problem arises when the folding stage known from U.S. Pat. No. 4,386,339 is to be used at high frequencies. The folding system implies that the frequency of the folding signal will be a multiple of the frequency of the input signal to be folded. The actual internal frequency is related both with the input frequency and the amplitude of the input signal. For example, an 8 times folding system requires a 125 MHz bandwidth at a maximum input frequency F.sub.in,max =10 MHz. At high speed operation these high frequencies lead to capacitive error signals in the folding signal caused by parasitic capacitances between the control electrode (gate or base) and first main electrode (source or emitter) of the transistors in the differentially coupled transistor pairs and by capacitances present at the common current source of the transistor pairs.